1. Field of the Invention
The present invention relates to the field of semiconductor memory and, more particularly, to testing of memory cells in semiconductor IC memory chips.
2. Description of the Related Art
FIG. 1 shows a typical computer memory system consisting of row decoders 10, column decoders 12, a memory array 14, sense amplifiers and write drivers 15 and a data buffer 16. Memory array 14 comprises individual memory cells arranged in rows and columns. Writing is accomplished by selecting an entire row (such as memory cells 100, 101 through 102) and selecting a column and by allowing data 19 to be written to the desired column. For each write cycle, only one memory cell is written because there is only one data buffer. During a normal operation, if there are 1,024 memory cells, it would require 1,024 write cycles to write the data to every memory cell. During a memory test operation, it is common to write a background pattern before running a specific test. In the example shown in FIG. 1, if there are 1,024 memory cells in memory array 14, since there is only one data buffer 16, it requires 1,024 write cycles to write a background pattern to memory array 14.
To reduce the number of write cycles required to write data to each memory cell, one can incorporate more data buffers as shown in FIG. 2. The computer memory system shown in FIG. 2 comprises row decoders 20, column decoders 22, memory array 24, sense amplifiers/write drivers 25 and data buffers 26. In this example, if there are 1,024 memory cells in memory array 24, it would require 256 (equal to 1,024 divided by 4) write cycles to write to each memory cell, and thus require 256 write cycles to write a background pattern to memory array 24. As one increases the number of data buffers, the number of required write cycles can be reduced. However, the number of data buffers is limited to the width of a data bus and the amount of realistic area that can be designated for data buffers. In the example shown in FIG. 2, there are four data buffers and the width of the data bus is four. Because of the limitation due to the width of the data bus and the realistic area available for data buffers on a chip (given that the transistor devices for these drivers should be large), it is not practical to include a large number of data buffers.
The present invention solves the problems stated above by incorporating a gang write circuitry consisting of small devices for writing a background pattern to memory cells during a memory test operation.